1. Field of the Invention
The present invention generally relates to the design process of integrated circuits and more particularly to a method and system for performing capacitance extraction that includes the effects of wiring not included in the data being extracted. This invention includes the effect of possible additional wiring during the calculation of capacitance using virtual wires and virtual fillshapes to increase efficiency.
2. Description of the Related Art
Conventional systems perform an xe2x80x9cextractionxe2x80x9d process which calculates the parasitic capacitance between the devices and wiring formed within an integrated circuit. Extraction processes that are performed on large, multi-level integrated circuit structures require large amounts of computing power. Therefore, many conventional methods are utilized to simplify the extraction process.
For example, some conventional systems divide the integrated circuit structure into different sections and/or levels of hierarchy. Each of the different sections and/or levels is extracted individually. The individual capacitances are then combined to find the overall parasitic capacitance of the circuit as a whole.
However, when performing a capacitance extraction upon a small portion of the overall integrated circuit design, many of the final wiring patterns (e.g. wiring which will eventually connect the different portions of the circuit) are not known because the remainder of the circuit has not yet been designed or is removed from the extraction data for efficiency. In order to make the capacitance calculation more accurate, the conventional systems must design and estimate the precise location and size of the wiring patterns that will be present after final assembly of the design and will impact each section of the circuit.
Often, the estimated wiring pattern cannot be known with certainty, which makes the parasitic capacitance calculation inaccurate. Further, the calculation and estimation of where the wiring patterns and fillshapes will be located is a cumbersome and time consuming process. These factors increase the cost and design time of conventional integrated circuits. Also the recognition of each edge of the environment increases the extraction effort significantly. Therefore, there is a need for a method and system which eliminates the requirement of adding wiring patterns to portions of an integrated circuit design when performing parasitic capacitance extraction procedures.
It is, therefore, an object of the present invention to provide a structure and method for performing capacitance extraction during the design of an integrated circuit, that includes inputting a specified wiring density and design requirements, determining a minimum spacing for wire segments based on the design requirements, calculating a transparency factor based on the wiring density, calculating a lateral capacitance assuming virtual wires are present in the integrated circuit, and calculating a vertical capacitance based on the transparency factor. The invention adds virtual wires to the integrated circuit where allowed by the minimum spacing. The virtual wires comply with the wiring density. The virtual wires are imaginary and are not included in a final design of the integrated circuit. The virtual wires only explain and motivate the change in the calculation of capacitance during extraction.
The invention also divides the integrated circuit into sections and performs the capacitance extraction on each of the sections independently. The virtual wires are theoretically added to each of the sections in order to include the capacitance effect of the other section onto the extracted circuit. As actual shapes are never created and extracted, the invention is much more efficient than conventional methods which have to resolve the actual edges of the environment conductors. The effect of the virtual shapes is evident during the calculation. Vertical fill shapes can be added and tied to the virtual shape node. Fill shapes also partially or completely screen vertical capacitance. Then the capacitance to the real shape is reduced with a transparency factor, which comprises a measure of capacitance screening of a layer within the integrated circuit. The part screened off is connected to virtual shapes node. The virtual shapes node is also used to add lateral capacitance to a circuit net.